1. Field of the Invention
This invention relates to a system and method for generating signals for adjusting the output frequency of an oscillation circuit such as a phase-locked loop.
2. Description of the Related Art
FIG. 1 shows a charge pump used in a conventional phase-locked loop. The charge pump includes an output stage 1 and a control stage 2. The output stage contains a differential arrangement of transistors Q1-Q4. Transistors Q2 and Q10 are the UP and DN current sources. Transistor Q2 is a switched current source, while transistors Q3 and Q4 implement the current switch for the Q10 current source. Transistor Q1 is the active load of the left branch in the differential structure. The gates of transistors Q2-Q4 are controlled by outputs of the control stage. A node N1 located between transistors Q2 and Q4 outputs source current Icharge to and sinks current Ipump from capacitor C1 of the loop filter. Sourcing or sinking this current for a time period proportional to the width of a control voltage pulse output from the charge pump causes the PLL to output a frequency signal that reduces the difference in phase between the reference and feedback signals.
The control stage 2 includes two input buffers B1 and B2 and transistors Q5-Q9. The buffers receive Up and Down signals and their complements (Up, Dn, Up#, Dn#) from the phase-frequency detector and output a corresponding In signal and its complement In# to control switching of the transistors in the output stage. When the left branch (Q5-Q7) is activated, the signal Vch from its Out# terminal swings DN (see FIG. 2) and controls the output of charge current Icharge to the loop filter. Buffer B2 directly outputs a down current source (pump) switching signal Vpm to transistor Q4 for controlling the sinking of current Ipump into node N1. The charge circuit, thus, has no dedicated switch (the “charge” current source is switched on and off) while the pump circuit has a dedicated switch (one directly controlled by the Dn/Dn# outputs of buffer B2). Transistors Q9 and Q10 receive a signal nbias for biasing the charge pump to a desired current value.
The conventional circuit described above generates charge and pump currents using switching signals that have different amplitudes and slew rates. Switching signal Vch is a low swing, slow slew rate signal having an amplitude determined by the PLL bias operating point. At low bias (low frequency), the amplitude is low and close to the threshold voltage of the P transistor Q2. At high bias (high frequency), the amplitude of Vch is increased. FIG. 2 shows these aspects of Vch, where curve A has a gradual slope indicative of a slow slew rate and an amplitude equal to the difference between Vcc and Vcntrl. In contrast to Vch, the down current (or pump) switching signal Vpm is a full rail, fast switching signal. This is evident from curve B in FIG. 3 which has a steep slope and an amplitude equal to the difference between Vcc and Vss. Using switching signals Vch and Vpm with different amplitudes and slew rates produces the following undesirable effects.
First, when a small phase error is input into the phase-frequency detector, the CHARGE state of the charge pump vanishes. Because the charge current source is switched by a slow, low swing analog signal (Vch), the charge circuit will not generate current at a sufficiently fast rate. As a result, the charge current Icp will be injected into the loop filter after the charge pump transitions to the OFF state. The charge current injected into the loop filter will therefore not look like a current pulse and thus the VCO output will not be controlled in the desired manner.
Second, parasitic switching currents (due to parasitic capacitances Cgd of the p-channel transistor Q2 of the n-channel transistor Q4) will flow to and from the loop filter capacitor C1 and affect the average charge pump current to zero for a non-zero input phase error. In a self-biased PLL such as shown in FIG. 4, the switching currents of the CP1 output stage are induced to the loop filter capacitor (C1), while the switching currents of the CP2 output stage are induced into the loop filter resistor. They generate spikes on V1 and Vcntl, thereby affecting the VCO frequency. This VCO frequency is the self-jitter of the PLL due to reference feed-through modulation. Techniques for implementing a self-biased PLL are disclosed in U.S. Pat. No. 6,329,882.
FIG. 5 shows the output current pulse produced by the conventional charge pump of FIG. 1 with zero phase error at the phase/frequency detector input. At zero phase error, the average of the output current should be zero. However, in FIG. 5, the average output current is not zero. The average current will be zeroed for a certain phase error, i.e., the PLL DC skew. Moreover, the output current appears as a high spike (Region A) indicative of instantaneous (feed-through) jitter.
The current waveform of FIG. 5 further indicates that the charge pump does not operate in a proper manner. For example, at zero phase error, the charge pump should work in OVERLAP mode. In this mode, both UP and DN current sources must be opened and thus the net current injected in capacitor C1 should be zero. However, as shown in FIG. 5, in the conventional circuit the UP current source opens late (Region B), i.e., at this point the UP current source should already be off.
The current waveform of FIG. 5 further shows that the switching currents through parasitic capacitors are high, and (due to differences in amplitude and slew rate of the controls) unequal. The net current due to these “parasitic” currents also have a major effect on the DC skew. More specifically, DC skew may be caused by two factors. First, because the charge pump does not operate correctly in OVERLAP mode, the contributions of the Up and Dn current sources are not equal, which results in a non-zero average. Second, the parasitic switching currents are not equal and do not cancel each other (due to non-equal amplitudes and slew rates of the control signals). Variance in process, temperature, and operating point results from these effects.
More specifically, since the amplitude of the Vch control signal is dependent on the bias operating point (that is, a function of operating frequency), temperature, and process, the net current injected into capacitor C1 (and thus the PLL DC skew) will highly vary with process, temperature, and operating frequency. (In the conventional circuit, the DC skew variation is typically 80 ps). The current spikes (which correspond to parasitic currents at Region A and point C) of CP2 determine voltage spikes on the loop filter resistor R, affecting the instantaneous VCO frequency (feed-through jitter).
In view of the foregoing considerations, it is clear that a need exists for an improved charge pump which may be implemented in a phase-locked loop, and more specifically one which does not realize the disadvantages of the conventional charge pump previously described.